Semiconductor devices are used for integrated circuits in a variety of electrical and electronic applications, such as computers, cellular telephones, radios, and televisions. One particular type of semiconductor device is a semiconductor storage device, such as a random access memory (RAM) device. Many RAM devices include many storage cells arranged in a two-dimensional array with two sets of select lines, wordlines and bitlines. An individual storage cell is selected by activating its wordline and its bitline. RAM devices are considered “random access” because any memory cell in an array can be accessed directly if the row and column that intersect at that cell are known.
A commonly used form of RAM is known as a dynamic RAM device. Dynamic random access memory (DRAM) has memory cells with a paired transistor and capacitor. DRAM devices store information as an electrical charge in the capacitor. One particular type of DRAM device is a synchronous DRAM (SDRAM) device. Synchronous dynamic random access memory often takes advantage of the burst mode concept to greatly improve performance by staying on the row containing the requested bit and moving rapidly through the columns. To achieve a high speed operation, a double data rate (DDR) architecture is often used, during which two data transfers are made per clock cycle, one upon the rising edge of the clock and the other upon the falling edge.
An individual memory cell for a DRAM usually comprises a capacitor of MOS structure for storing a charge representing the desired data. This stored charge tends to dissipate over time due to charge leakage from the capacitor. In order to prevent the stored data-bearing charge from being lost, it is known that the memory cells of DRAMs have to be regularly read and then have their contents rewritten, which is referred to as a “refresh” of the memory cells. Each of the memory cells in a DRAM device must be periodically refreshed in this manner, wherein the maximum refresh period is determined by a variety of process parameters and is defined by the device manufacturer typically in accordance with predetermined standards.
Practical DRAM devices may have on chip control logic for automatically carrying out an externally or internally generated refresh command. The on chip refresh logic would make the refresh process transparent to the user by inputting a refresh command from, for example, a memory controller, and internally carrying out all the logical steps necessary to refresh some or all of the memory cells in the allotted time period, including address generation, wordline and bitline activation, and returning the chip to a precharge state.
The requirement to refresh a DRAM is integral to the MOS-capacitor structure of the individual memory cells, and this refresh operation takes some time to perform. The refresh operation reduces the overall throughput of the DRAM, as the DRAM is typically unavailable for data read and write operations during refresh. It is therefore advantageous to minimize the amount of time that must be spent refreshing the memory cells, as the refresh time represents a dead time in the operation of the memory device.
There are a variety of circuits, systems, and methods for refreshing DRAM devices known in the art. Among these are U.S. Pat. No. 6,643,205, “Apparatus and method for refresh and data input device in SRAM having storage capacitor cell”, issued to Kim; U.S. Pat. No. 6,625,077, “Asynchronous hidden refresh of semiconductor memory”, issued to Chen; U.S. Pat. No. 4,943,960, “Self-refreshing of dynamic random access memory device and operating method therefore”, issued to Komatsu, et al.; U.S. Pat. No. 6,363,024, “Method for carrying out auto refresh sequences on a DRAM”, issued to Fibranz; U.S. Pat. No. 5,995,434, “Dynamic random access memory device having a self-refresh mode”, issued to Ryu; U.S. Pat. No. 6,567,332, “Memory device with reduced power consumption refresh cycles”, issued to Sawhney; and U.S. Pat. No. 6,661,732, “Memory system having reduced powder data refresh” issued to Sunaga. All of the above listed patents are incorporated herein by reference in their entirety.